Sensitive test structure for assessing pattern anomalies

ABSTRACT

A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

FIELD OF INVENTION

The present invention relates generally to semiconductor technologiesand more particularly to a test structure and methodology for developingand utilizing the same to detect process drift and/or pattern anomaliesin semiconductor processing.

BACKGROUND OF THE INVENTION

The widespread proliferation of computers and electronic devices iscontinually increasing as computers are consistently being used fordifferent and more sophisticated applications. For example, the growthand use of digital media (e.g., digital audio, video, images, and thelike) has expanded the use of computers, as well as the volume andcomplexity of functionality needed to be supported by these devices.Likewise, new and improved electronic devices (e.g., digital audioplayers, video players) are continually being developed and are placingnew and ever increasing demands on the technology behind these devices.This growth and development has vastly increased the processing andstorage needs for computer and electronic devices, as well as the desireto produce these devices in a manner that allows such devices to be madeavailable to consumers at affordable prices.

Accordingly, in the semiconductor industry, there is a continuing trendtoward higher densities, throughput and yield. To achieve highdensities, there has been and continues to be efforts toward scalingdown dimensions (e.g., at submicron levels) on semiconductor wafers,which are generally produced from bulk silicon. In order to accomplishsuch high packing densities, smaller feature sizes and more precisefeature shapes are required in integrated circuits (ICs) fabricated onsmall rectangular portions of the wafer, commonly known as dies. Thismay include the width and spacing of interconnecting lines, spacing anddiameter of contact holes, as well as the surface geometry of variousother features (e.g., corners and edges). The dimensions of features andthe spacing therebetween can be referred to as critical dimensions(CDs). Reducing CDs, and reproducing more accurate CDs facilitatesachieving higher densities through scaled down dimensions and increasedpacking densities. To increase throughput, the number of requiredprocessing steps can be reduced and/or the time required to performthose processing steps can be reduced. To increase yield, which is thepercentage of finished products that leave a fabrication process ascompared to the volume of raw materials that enter the fabricationprocess, quality control over individual fabrication processes can beimproved.

In semiconductor fabrication a wafer is entered into a processingchamber and exits from the chamber with hundreds of copies (or more) ofone or more features formed onto the wafer, and more particularly ontorespective die of the wafer. During the fabrication process the wafermay be subjected to hundreds of steps that may include, for example,layering, doping, heat treating, patterning, deposition, growth,alignment, illumination, exposure, magnification/de-magnification,focusing, baking, developing, etching, patterning, implanting,polishing, reacting, and others, by which one or more transistors and/orother electrical devices are formed and interconnected on die on thewafer.

By way of example, multiple iterations of manipulating thin films may beperformed to create several patterned layers on and into a substrate ofthe wafer. Layering is an operation that adds thin layers to the wafersurface. Layers can be, for example, insulators, semiconductors and/orconductors and are grown or deposited via a variety of processes. Commondeposition techniques include, for example, CVD, sputtering and/orelectroplating. Doping is another operation wherein a specific amount ofdopants are selectively added to the wafer. The dopants can cause theproperties of layers to be modified (e.g., change a semiconductor to aconductor). A number of techniques, such as thermal diffusion and ionimplantation can be employed for doping. Heat treatments are anotherbasic operation in which a wafer is heated and cooled to achievespecific results. Typically, in heat treatment operations, no additionalmaterial is added or removed from the wafer, although contaminants andvapors may evaporate from the wafer. One common heat treatment isannealing, which activated dopants and repairs damage to the crystalstructure of a wafer/device generally caused by doping operations. Otherheat treatments, such as alloying and driving of solvents, are alsoemployed in semiconductor fabrication.

By performing these steps, the fabrication process selectively formsdesired structures or features at specific locations in and on die ofthe wafer. These structures or features may comprise, for example,electrically active regions of integrated circuits formed on the wafer.The layer to layer orientation or registration, size, location, shapeand isolation of such electrically active structures affects thereliability and performance of resulting integrated circuits employingsuch structures. For example, registration error, mis-alignment,mis-patterning, or other pattern anomalies that can result from processdrift or other undesirable processing conditions can compromise theperformance of the structures and adversely affect resulting chipperformance and reliability.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an extensive overview of the invention. It is intendedneither to identify key or critical elements of the invention nor todelineate the scope of the invention. Rather, its purpose is merely topresent one or more concepts of the invention in a simplified form as aprelude to the more detailed description that is presented later.

One or more aspects of the present invention pertain to a subset testmodule and associated methodology for utilizing the same that facilitateidentification of process drift in semiconductor fabrication processing.A test wafer having a plurality of die formed thereon has a plurality oftest modules formed within each die. The plurality of test modules aresubstantially the same from die to die. The respective modules similarlyinclude a plurality of test structures that are substantially the samefrom module to module. Corresponding test structures within respectivemodules on different die can be inspected and compared to one another tofind those structures that are sensitive to process drift. One or morestructures that experience substantial differences or variations frommodule to module on different die are utilized to develop one or moretest modules that can be selectively located within production wafersand monitored during semiconductor processing to determine whetherprocess drift and/or one or more other aberrant processing conditionsare occurring.

According to one or more aspects of the present invention, a method offashioning one or more test modules suitable for implementation with asemiconductor fabrication system to monitor for semiconductorfabrication process drift includes forming one or more test modules indie on a test wafer, wherein respective test modules in different dieinclude similar sets of test structures. The method also includesinspecting one or more of the test structures in one or more of the testmodules on one or more of the die, and comparing inspected teststructures of one or more die to corresponding test structures in one ormore other die. The method further includes determining whetherdifferences exist between the inspected corresponding test structuresand then generating one or more subset test modules comprising inspectedstructures that differed substantially from die to die and thus indicatea sensitivity to process drift or other changes in processingconditions.

In accordance with one or more other aspects of the present invention,the method further includes utilizing one or more of the subset testmodules to determine process drift by incorporating one or more of thesubset test modules within a production wafer undergoing the fabricationprocess, monitoring one or more features within one or more of thesubset modules, comparing corresponding features from one or more subsetmodules to another and determining that process drift may be occurringwhere corresponding features vary between one or more subset modules.

According to one or more other aspects of the present invention, a testwafer suitable for use in developing one or more subset test modulesthat are themselves suitable for use in a semiconductor fabricationprocess to facilitate a determination of process drift includes one ormore die, wherein the respective die have a plurality of test modulesformed thereon that are substantially the same from die to die. Thecorresponding test modules on the respective die have a plurality oftest structures formed thereon that are substantially the same frommodule to module. Differences in corresponding test structures oncorresponding test modules may be indicative of process drift, and oneor more subset test modules may be generated from one or more teststructures that exhibit differences indicative of process drift.

In accordance with one or more further aspects of the present invention,a mechanism suitable for incorporation into a production wafer tofacilitate a determination of semiconductor fabrication process driftincludes one or more subset modules comprising a plurality of teststructures formed thereon. The test structures are sensitive to processdrift or other aberrant processing conditions, wherein the plurality oftest structures are substantially the same among at least some of thesubset modules, and wherein detected differences between correspondingtest structures provide an indication that process drift or otheraberrant processing conditions are occurring.

To the accomplishment of the foregoing and related ends, the followingdescription and annexed drawings set forth in detail certainillustrative aspects and implementations of the invention. These areindicative of but a few of the various ways in which one or more aspectsof the present invention may be employed. Other aspects, advantages andnovel features of the invention will become apparent from the followingdetailed description of the invention when considered in conjunctionwith the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating the layout of a test wafer inaccordance with one or more aspects of the present invention.

FIG. 2 is a schematic diagram illustrating the layout of a die inaccordance with one or more aspects of the present invention.

FIG. 3 is a plan view of a portion of a die on a wafer illustrating anexemplary test structure or test feature in accordance with one or moreaspects of the present invention.

FIG. 4 is a system level diagram illustrating a test system, wherein atest wafer is implemented in accordance with one or more aspects of thepresent invention.

FIG. 5 is a schematic illustration depicting a top view of an exemplaryportion of a die that may be included on a test wafer, such as thatdepicted in FIG. 1, or on a production wafer according to one or moreaspects of the present invention.

FIG. 6 is a schematic diagram illustrating a cut away side view of aportion of the die depicted in FIG. 5, taken along dotted line 6-6.

FIG. 7 is a schematic diagram illustrating a cut away side view of aportion of the die depicted in FIGS. 5 and 6 demonstrating how one ormore structures are formed thereon.

FIG. 8 is another schematic diagram illustrating a cut away side view ofa portion of the die depicted in FIGS. 5 and 6 demonstrating how one ormore structures are formed thereon.

FIG. 9 is yet another schematic diagram illustrating a cut away sideview of a portion of the die depicted in FIGS. 5 and 6 demonstrating howone or more structures are formed thereon.

FIG. 10 is still another schematic diagram illustrating a cut away sideview of a portion of the die depicted in FIGS. 5 and 6 demonstrating howone or more structures are formed thereon.

FIG. 11 is a schematic block diagram illustrating an exemplary systemsuitable for inspecting a test wafer comprising an arrangement accordingto one or more aspects of the present invention, such as that describedwith respect to FIGS. 5-10.

FIG. 12 is a schematic illustration depicting a top view of an exampleof a portion of a die that may be included on a test wafer, such as thatdepicted in FIG. 1, or on a production wafer in accordance with one ormore aspects of the present invention.

FIG. 13 is a schematic diagram illustrating a cut away side view of aportion of the die shown in FIG. 12, taken along dotted line 13-13.

FIG. 14 is a schematic diagram similar to that of FIG. 13, illustratinga cut away side view of a portion of a die that may be included on atest wafer, such as that depicted in FIG. 1, or on a production wafer inaccordance with one or more aspects of the present invention.

FIG. 15 is a block diagram that illustrates detection of situations suchas that described with respect to FIGS. 12-14 according to one or moreaspects of the present invention.

FIG. 16 is a schematic diagram illustrating the layout of a productionwafer in accordance with one or more aspects of the present invention.

FIG. 17 is a schematic diagram illustrating a cut away side view of aportion of a die, such as that depicted in FIG. 16 according to one ormore aspects of the present invention.

FIG. 18 is a schematic block diagram illustrating an exemplarysemiconductor fabrication system wherein test structures may beimplemented in accordance with one or more aspects of the presentinvention to identify process drift and/or pattern anomalies.

FIG. 19 is a schematic diagram of a random section of a test modulehaving a plurality of test structures formed therein in accordance withone or more aspects of the present invention.

FIGS. 20-22 are schematic diagrams similar to that shown in FIG. 19wherein potential problem areas are identified.

FIG. 23 illustrates a flow diagram of a methodology for fashioning andutilizing a test module in accordance with one or more aspects of thepresent invention to monitor for process drift and/or other aberrantbehavior in semiconductor fabrication processing.

DETAILED DESCRIPTION OF THE INVENTION

One or more aspects of the present invention are described withreference to the drawings, wherein like reference numerals are generallyutilized to refer to like elements throughout, and wherein the variousstructures are not necessarily drawn to scale. In the followingdescription, for purposes of explanation, numerous specific details areset forth in order to provide a thorough understanding of one or moreaspects of the present invention. It may be evident, however, that oneor more aspects of the present invention may be practiced with a lesserdegree of these specific details. In other instances, structures anddevices are shown in block diagram form in order to facilitatedescribing one or more aspects of the present invention.

It is to be appreciated that various aspects of the present inventionmay employ technologies associated with facilitating unconstrainedoptimization and/or minimization of error costs. Thus, non-lineartraining systems/methodologies (e.g., back propagation, Bayesian, fuzzysets, non-linear regression, or other neural networking paradigmsincluding mixture of experts, cerebella model arithmetic computer(CMACS), radial basis functions, directed search networks and functionlink networks) may be employed.

The term “component” as used herein is intended to includecomputer-related entities, either hardware, a combination of hardwareand software, software, or software in execution. For example, acomponent may be a process running on a processor, a processor, anobject, an executable, a thread of execution, a program, a computer, orany combination thereof. By way of illustration, both an applicationprogram running on a server and the server can be components.

One or more aspects of the present invention relate generally to asubset test module and associated methodology for utilizing the samethat facilitate identification of process drift in semiconductorfabrication processing. A test wafer having a plurality of die formedthereon has a plurality of test modules formed within each die. Theplurality of test modules are substantially the same from die to die.The respective modules similarly include a plurality of test structuresthat are substantially the same from module to module. Correspondingtest structures within respective modules on different die can beinspected and compared to one another to find those structures that aresensitive to process drift. One or more structures that experiencedifferences from module to module on different die are utilized todevelop one or more test modules that can be selectively located withinproduction wafers and monitored during semiconductor processing todetermine whether process drift and/or one or more other aberrantprocessing conditions are occurring.

FIG. 1 is a schematic diagram illustrating the layout of a test wafer100 in accordance with one or more aspects of the present invention. Thewafer 100 has a plurality of die 102 located thereon. Enlargedrepresentations of a couple of the die illustrate an arrangementaccording to one or more aspects of the present invention wherein eachdie possess a plurality of test modules (TMs) 104 formed therein. Inparticular, each of the die (or at least a significant number thereof)includes the same arrangement of test modules TM1-TMN, where N is apositive integer.

Additionally, in the exemplary structure illustrated, the test modules104 within each die differ in size, such that TM2 has one or morefeatures that are smaller than those associated with TM1, and TMNfeatures are smaller than those in TM2. It will be appreciated, however,that the ordering of the different size test modules 104 is arbitrary,and that the particular ordering depicted in FIG. 1 is done forexemplary purposes only. For example, TM2 can be smaller than TMN, andTM1 can be smaller than TM2. Likewise, TM2 can be smaller than both TM1and TMN, where TM1 is smaller than TMN, etc. This will be discussed ingreater detail below.

FIG. 2 is a schematic diagram illustrating the layout of an exemplarydie 102 in accordance with one or more aspects of the present invention.The die 102 is representative of the die depicted in FIG. 1, and mayaccordingly be located on a wafer along with a plurality of similarlyconfigured die. The die 102 includes a plurality of test modulesTM1-TMN, where N is a positive integer. Enlarged representations of thetest modules 104 reveal that they include a plurality of respective teststructures (TS) TS1-TSP or test features, where P is a positive integer.

It can be seen that the test structures 106 differ/are reduced in sizefrom one test module 104 to the other. As set forth in the precedingdiscussion of the test modules, it will be appreciated, however, thatthe ordering of the different size test structures is arbitrary, andthat the particular ordering illustrated is exemplary only. For example,the size of the test structures in test module TM2 can be smaller thanthe test structures in test module TMN, and the test structures in testmodule TM1 can be smaller than the test structures in test module TM2.Similarly, the test structures in test module TM2 can be smaller thanthe test structures in both test module TM1 and the test structures intest module TMN, where the test structures in test module TM1 aresmaller than the test structures in test module TMN, etc.

It will be appreciated that the test structures 106 can be sizedaccording to design rules, which dictate characteristics to which thedevices can be made to ensure certain predetermined performance orreliability characteristics for a given process. For example, the designrules for a particular semiconductor process may dictate that aparticular structure or feature within the device is to have a certainminimum dimension (e.g., width) to ensure that the device performs witha desired reliability.

Accordingly, the test structures 106 (and thus the test modules 104) canbe sized in incremental percentages of a design rule. In the illustratedexample, the test structures TS1-TSP of the first test module are formedaccording to one hundred percent of the design rule. The test structuresTS1-TSP of the second test module are formed according to ninety sevenpercent of the design rule. And, the test structures TS1-TSP of the Nthtest module can be formed according to a lesser percent of the designrule, etc. It will be appreciated, however, that these figures areexemplary only and that the test structures (and thus the test modules)can be sized according to any variations of a design rule. For example,the test structures can be sized so that one or more of them exceed onehundred percent of the design rules.

Turning to FIG. 3, a top down schematic view of a portion of a die 300on a wafer includes an exemplary test structure or test feature 304. Theinstances of the exemplary test structure shown depict a gate patternwherein two conductive materials 306, 308 are separated by anon-conductive dielectric material 310. More particularly, the structureshown may correspond to a gate of 0.09 microns, for example, where polygate leads form a discontinuous T-shape. Electrical bridging can occurin such patterns where the gates are formed too close to one anotherand/or unintentionally touch or are too close resulting in dielectricreliability issues. Such a situation may occur, for example, as a resultof optical proximity errors or process drift.

In the example shown, the test structures 304 are labeled to correspondto the first test structure TS1 replicated in each of the test modulesTM1-TMN illustrated in FIG. 2. Thus, FIG. 3 illustrates a test structureor feature 304 that is repeated on N different test modules, but hassizing differences in each of the modules. More particularly, a spacingbetween the poly features 306, 308 differs among the test structures.From left to right, the poly spacing is reduced from one test structureto the next. The poly spacing in the first module TM1 may, for example,correspond to one hundred percent of a design rule, while the spacing inthe second and Nth modules (wherein N=3) may correspond to ninety sevenand ninety four percent of the design rule, respectively.

FIG. 4 illustrates a test system 400, wherein a test wafer 402 isimplemented in accordance with one or more aspects of the presentinvention. The test wafer 402 and its arrangement is similar to thatdepicted in FIGS. 1-3 and thus has a plurality of die 404 formedthereon. All or at least most of the die 404 also have a plurality oftest modules (e.g., 1-N, where N is a positive integer) formed thereon(not shown), and the test modules themselves have a plurality of teststructures or test features (e.g., 1-P, where P is a positive integer)formed thereon (not shown).

An inspection system 406 is included to facilitate a determination ofwhether a particular test structure is sensitive to changes in processconditions. More particularly, the inspection system facilitates acomparison of test structures or features in one die to the samestructures in an adjacent die. If there is a substantial difference,then this may be indicative of a suspicious point. By way of example,should corresponding test structures differ by a predetermined amount oraccording to other predefined criteria, then a certain sensitivitydesignation can be assigned to the subject feature(s). An optical toolor an electrical test tool, for example, can be utilized to interrogatea first test structure on a first test module located on a first die.The same test structure on a similar test module located on a second diecan similarly be inspected. This can be done for any number ofstructures on any number of test modules located on any number of die404. By way of example, the test modules can have hundreds of differenttypes of structures and/or feature combinations located thereon.Measured values of the same structures taken from similar test moduleslocated on different die can then be compared to determine sensitivityof test structures to operating conditions. More particularly, one ormore differences in these values may be indicative of a structure thatis sensitive to changes in processing conditions, process drift orsubtle production abnormalities.

It will be appreciated that, as described above, the test structures canbe sized differently to identify enhanced sensitivity. For example, thetest structures and thus the test modules can be replicated in smallerand smaller increments, such as by about three percent of the designrule or so, so that a first test module on a die is a particular sizeaccording to a design rule, a second test module on the same die isninety seven percent of this size, a third test module on the die isninety four percent of this size, a fourth test module on the die isninety one percent of this size, etc. This facilitates finding thosefeatures that are prone to failures (e.g., shorts or opens) due tovariations in processing conditions, such as alignment, layer thickness,layer flatness, layer (non) uniformity, illumination intensity, focuscontrol, degree of focus, developer conditions, etch characteristics(e.g., composition), etc. Generally speaking, smaller features are morelikely to exhibit anomalous behavior under certain circumstances. Itwill be further appreciated that gradual reductions in feature sizes(e.g., by about three percent or so) allow sensitive features to beidentified while mitigating the risks of exposing a wafer tocontaminants. Drastic reductions in feature sizes (e.g., of about twentypercent or more) are preferably avoided because such reductions can, forexample, cause features to be printed very poorly, such that thefeatures may lift off of a substrate and become floating contaminantsthat can cause damage to other parts of a wafer in production.

It will also be appreciated that the inspection system 406 can be astand alone component and/or can also be distributed between two or morecooperating devices and/or processes. Similarly, the inspection system406 can reside in one physical or logical device (e.g., computer,process) and/or be distributed between two or more physical or logicaldevices. The inspection system 406 includes one or more non-destructivemeasurement components adapted to take readings of the test structures.The inspection system is operatively coupled to a control system 408that can be configured in any suitable manner to control and operate thevarious components within the system 400 in order to carry out thevarious functions described herein. For example, the control system 408may provide one or more signals to the inspection system to control atleast some of the operations of the inspection system. Similarly, thecontrol system 408 is adapted to receive signals from the inspectionsystem 406 indicative of readings taken by the inspection system 406.Such readings may, for example, be related to critical dimensions,conductivity, resistivity, etc. of the test structures.

In the example shown, the control system 408 includes a processor 410,such as a microprocessor or CPU, coupled to a memory 412. The processor410 can be any of a plurality of processors, and the manner in which theprocessor 410 can be programmed to carry out the functions relating tothe present invention will be readily apparent based on the descriptionprovided herein. The memory 412 included within the control system 408serves to store, among other things, program code executed by theprocessor 410 for carrying out operating functions of the system 400 asdescribed herein. The memory 412 may include read only memory (ROM) andrandom access memory (RAM). The ROM contains among other code the BasicInput-Output System (BIOS) which controls the basic hardware operationsof the system 400. The RAM is the main memory into which the operatingsystem and application programs are loaded. The memory 412 may alsoserve as a storage medium for temporarily storing information such as,for example, tabulated data and algorithms that may be employed incarrying out one or more aspects of the present invention. The memory412 can also serve as a data store (not shown) and can hold, forexample, patterns against which observed data can be compared as well asother data that may be employed in carrying out the present invention.For mass data storage, the memory 412 may include a hard disk drive.

A collection or subset of features or elements 414 that are highlysensitive to process variations and that are dimensioned so as to havean increased sensitivity can thus be identified and output by the system400. Since the subset 414 comprises less than all of the features in theoriginal test module, the size of the subset of features may be smallenough to be formed within a scribe line or other unused available space(e.g., “white space”) within a production wafer (e.g., on a die, betweendie, between elements within a die) to monitor process drift. The subsetof test structures 414 would thus have its own set of design rules thatare smaller than production design rules to expose process variations ordrift.

It will be appreciated that the particular makeup of the subset offeatures 414 may be dependent upon the process under which the teststructures were analyzed. For example, a BiCMOS process may yield asubset of features different than that produced by an embedded memoryprocess because different processes operate under different conditions.Accordingly, the test structure may be developed under controlledvariations in processing conditions to provide an indication as to whichprocessing conditions have the greatest impact on particular features.This facilitates identifying which processing conditions a detectedprocess drift may be attributable to. For example, anomalous behaviordetected within certain features may be indicative of particular processcondition(s) that may need to be readjusted. These can then be focusedin on and examined to determine whether, in fact, they are behavingabnormally, and, if so, what adjustments can be made to mitigate theproblem. For example, aberrant readings obtained from one particularfeature during a particular type of processing (e.g., BiCMOSfabrication) may be indicative of deviations in illumination intensity.Accordingly, that feature and/or surrounding features may be monitoredmore closely to determine the extent to which exposure should beincreased or decreased to achieve a desired result during thephotolithography fabrication process.

By way of further example, FIGS. 5-13 illustrate additional situationsthat can be identified according to one or more aspects of the presentinvention. FIG. 5 is a schematic illustration depicting a top view of aportion of a die 500 that may be included on a test wafer, such as thatdepicted in FIG. 1, or on a production wafer. Two regions of the die502, 504 include an electrically active/conductive material, such ascopper. These regions 502, 504 may, for example, be part of anintegrated circuit formed upon the die. These regions do not appear tobe electrically coupled to one another. Thus, a visual inspection ofthis arrangement from a top view, such as that presented in FIG. 5,would not reveal an unintended electrical coupling between these tworegions.

Turning to FIG. 6, however, which is a schematic diagram illustrating across-section of a portion of the die 500 shown in FIG. 5 taken alongthe dotted line 6-6. It will be appreciated that an electricallyactive/conductive material 506 can in fact exist between these tworegions 502, 504 on a lower layer of the die. FIGS. 7-10 are schematicdiagrams illustrating a cross-section of a portion of the die 500, anddemonstrate just how such an undesirable electrical connection can beformed within a wafer (e.g., due to under etching and/or underpolishing). FIG. 7 illustrates that respective trenches 508, 510 for theregions can be formed (e.g., etched) into a couple of layers of the die,which are themselves formed upon another layer 512 (e.g., a bottomsubstrate layer). In FIG. 8, a layer 514 of the conductive material canthen be formed over the layers to fill the trenches. FIG. 9 shows thatthe layer of conductive material can then be etched and/or polished awayto leave the apertures filled with the conductive material. However,under etching and/or under polishing can leave a trace amount 506 (shownenlarged for purposes of simplicity) of the conductive material betweenthese conductive regions. FIG. 10 shows that additional layer(s) 516 canthen be formed over the existing layers. These additional layers canthen be etched and filled with conductive material to establish theconfiguration depicted in FIG. 6, wherein the electrically activeregions are undesirably, but unnoticeably, interconnected by residualmaterial 506.

FIG. 11 is a schematic block diagram illustrating an exemplary system1100 suitable for inspecting a test wafer comprising an arrangement suchas that described above with respect to FIGS. 5-10. The system 1100utilizes scanning electron microscope (SEM) technology and includes achamber 1102 for housing a wafer 1104 or a sample portion thereof duringinspection. An electron beam 1106 is created from a high voltagesupplied by a power supply 1108 associated with a beam generating system1110, which includes an emission element 1112. Various directing,focusing, and scanning elements (not shown) in the beam generatingsystem 1110 guide the electron beam 1106 from the emission element 1112to an electromagnetic lens 1114. The beam 1106 is then directed from thelens 1114 toward the sample portion 1104. As the electron beam 1106strikes the wafer 1104, secondary electrons and x-rays are emitted whichare detected by a detector 1116 and are provided to a detection system1118.

The detection system 1118 provides digitized detector signals to aprocessing system 1120 for performing measurement and signal analysis,by which an image of the scanned sample 1104 may be generated. The imagemay then be directed to a display 1122 by the processing system 1120.Contrast of the displayed image is related to variations in the flux ofelectrons arriving at the detector 1116 and is related to the yield ofemitted electrons from the wafer 1104 to the incident electrons from theelectron beam 1106.

The detection system 1118 receives the electron emissions from thesample 1104 via the detector 1116 and preferably digitizes theinformation for the processing system 1120. The processing system 1120provides critical dimension information to the display 1122 and/orstores information in a memory 1124. A processor (not shown) is includedin the processing system 1120 for controlling the beam generating system1110, providing critical dimension measurements, and for performingsignal analysis. The processor in the processing system 1120 isprogrammed to control and operate the various components within thesystem 1100 in order to carry out various inspection and displayfunctions.

The memory 1124 is operatively coupled to the processing system 1120 andserves to store program code executed by the processor for carrying outoperating functions of the system 1100, and serves as a storage mediumfor temporarily storing information such as critical dimension data orother data. The power supply 1108 may be any power supply (e.g., linear,switching) suitable for carrying out one or more aspects of the presentinvention.

By way of still further example, FIGS. 12-14 illustrate additionalsituations that can be identified in accordance with one or more aspectsof the present invention. FIG. 12 is a schematic illustration depictinga top view of a portion of a die 1200 that may be included on a testwafer, such as that depicted in FIG. 1, or on a production wafer. Tworegions 1202, 1204 of the die include an electrically active/conductivematerial, such as copper. These regions may, for example, be part of anintegrated circuit formed upon the die.

FIG. 13 is a schematic diagram illustrating a cross-section of theportion of the die 1200 shown in FIG. 12 taken along the dotted line13-13. It can be seen that the conductive regions are formed byrespective vias that are filled with the conductive material. A lower1206 layer (e.g., substrate) of the die in this example is connected toground, and facilitates connecting the conductive regions to ground. Theupper contact area 1208 of the left conductive region 1202 is not,however, supposed to be connected to ground by way of the conductivefilament 1212 through dielectric layer 1210. Dielectric layer 1210 issupposed to be continuous over the underlying layer 1202 preventingelectrical connection of 1208 to ground. The right conductive region1204 is similarly mis-connected in the example shown. More particularly,the entirety of the right conductive region 1204 is supposed to becoupled to ground. However, it is not connected to ground by virtue ofan unwanted void 1214 present within the via.

FIG. 14 is a schematic diagram similar to that of FIG. 13, illustratinga cut away side view of a portion of a die 1400 that may be included ona test wafer, such as that depicted in FIG. 1, or on a production wafer.Two vias are filled with a conductive material, such as copper, to formtwo electrically active/conductive regions 1402, 1404 within the diethat may, for example, be part of an integrated circuit formed upon thedie. Similar to the situation depicted in FIGS. 5-10, however, the twoelectrically active regions 1402, 1404 are interconnected by an unwantedstrip 1406 of conductive material that remains due to insufficientpolishing and/or etching, for example. And, as discussed above withregard to FIGS. 12 and 13, a lower 1408 (e.g., substrate) layer of thedie 1400 is coupled to ground, and facilitates connecting the conductiveregions to ground. While the right conductive region 1404 is intended tobe connected to ground, the left conductive region 1402 is not designedto be connected to ground, and yet it is, due to the strip of material1406 that electrically interconnects the left and right conductiveregions 1402, 1404.

FIG. 15 is a block diagram that illustrates a system 1500 that can beutilized to detect situations such as that described with respect toFIGS. 12-14 according to one or more aspects of the present invention.The system relies on voltage contrast aspects, or the nature of whathappens when an electron beam is utilized to inspect structures that aregrounded, partially grounded or not grounded. Accordingly, the systemutilizes an electron beam monitoring or inspection system 1502 thatdirects an electron beam 1504 at structures 1506, 1508 to be measured,and outputs the results of measurements to a processor for furtheranalysis and/or to a display 1510 whereon they can be presented to auser.

In the example shown, the electron beam 1504 is directed at a portion ofa wafer that has the electrically active regions 1506, 1508 formedthereon. It will be appreciated that the portion may correspond to aportion of a die on a wafer, such as that depicted in FIGS. 1, 5, and12-13. Structures that are grounded will bleed out charge from theelectron beam and appear bright on the display. Structures that are notgrounded will accumulate charge and act as an open circuit or a largeresistor and appear as a different color and/or shade on the display.Thus, features that are grounded which should not be grounded orfeatures that are not grounded which should be grounded can beidentified. By way of example, the portion of the wafer illustrated inFIG. 15 can correspond to that depicted in FIG. 13. Accordingly, theelectron beam inspection discloses the aforementioned defects bypresenting the left conductive region 1506, which is unintentionallygrounded, as a light strip on the display 1510, while presenting theright conductive region 1508, which is unintentionally open or notgrounded, as a darker strip on the display 1510. Through a comparison ofcorresponding test structures from die to die (e.g., for a determinationof whether they differ/bleed out charge by a predetermined amount), thisinformation can be utilized to designate the subject test structures ashaving a particular sensitivity to the instant operating conditions.

FIG. 16 is a schematic diagram illustrating the layout of a productionwafer 1600 in accordance with one or more aspects of the presentinvention. The wafer 1600 has a plurality of die 1602 located thereon(with scribe lines shown enlarged for purposed of simplicity), as wellas a plurality of subset test modules STM1-STMQ, where Q is a positiveinteger, located therein. Enlarged representations of a couple of thesubset test modules 1604 reveal that that the test modules 1604 containa plurality of test structures TS1-TSR, where R is a positive integer.The respective structures or features 1606 within the subset testmodules 1604 are highly sensitive to process variations and are selectedaccording to the process discussed supra. Such subsets can, for example,correspond to those produced in accordance with the discussion relatingto FIG. 4. Accordingly, the test modules 1604 are small enough to beformed within scribe lines 1608 with the wafer 1600, as shown in theillustrated example. It will be appreciated, however, that the testmodules 1604 can be located at any suitable locations on the wafer 1600,including within white or unused spaces of the die 1602.

By way of example, FIG. 17 is a schematic diagram illustrating a cutaway side view of the portion of a die 1700, such as that which may bedepicted in FIG. 16. The die comprises a plurality of layers 1702, and aplurality of subset test modules STM1-STMS, where S is a positiveinteger, that are randomly scattered throughout a depth of the die 1700.It is to be appreciated that the subsets of test features 1704 may bedesigned for implementation with particular fabrication processes. Forexample, the particular makeup of the subsets of features may bedependent upon the process under which the test structures wereanalyzed. For example, a BiCMOS process may yield a subset of featuresdifferent than that produced by an embedded memory process becausedifferent processes operate under different conditions. Accordingly, thetest structures may correspond to or be more sensitive to particularprocessing conditions. It is to be further appreciated that all of thesubset test modules need not contain the same test structures. Thisfacilitates monitoring a greater variety of processing conditions.Additionally, subset test modules 1704 that comprise different teststructures may differ in size. Since the test structures may reside atdifferent points in the process, evaluation of the different structuresmay also be performed at differing process stages.

FIG. 18 is a schematic block diagram illustrating an exemplarysemiconductor fabrication system 1800 wherein test structures may beimplemented in accordance with one or more aspects of the presentinvention to identify process drift and/or pattern anomalies. A wafer1802 similar to that described above with respect to FIGS. 16 and 17having a plurality of die 1804 formed thereon and a plurality of subsettest modules 1806 formed therein (e.g., within scribe lines 1808) isincluded within a processing chamber 1810. The chamber 1810 includes asupport 1812, such as may include a stage (or chuck) operative tosupport the wafer 1802. A positioning system 1814 is operativelyconnected to the support 1812 for selectively maneuvering the wafer 1802within the chamber 1810.

A control system 1816, fabrication components 1818 and a measurementsystem 1820 are also included in the exemplary system, as are a powersupply 1822, display 1824 and data store 1826. The power supply 1822 isincluded to provide operating power to one or more components of thesystem 1800. It will be appreciated that any suitable power supply 1822(e.g., battery, line power) can be employed to carry out the presentinvention. The display 1824 is operable to present relevant informationto a user (e.g., graphical depictions of measured values). The datastore 1826, discussed in greater detail below, is operable to bepopulated with data that may be utilized by the system. In theillustrated example, the control system 1816 is operatively coupled tothe measurement system 1820, the fabrication components 1818, thepositioning system 1814, the display 1824 and the data store 1826 forselectively controlling the same. For example, the control system 1816can selectively control the fabrication components 1818 and/or one ormore operating parameters associated therewith (e.g., via feed forwardand/or feedback) based upon readings taken by the measurement system1820.

The measurement system 1820 can include, for example, a scanningelectron microscope (SEM) which interacts with structures within thesubset test modules 1806 as described above to measure and ascertaincritical dimensions, registration error, mis-patterning and/or otheraspects of the structures to monitor and control the fabrication processwhile mitigating the amount of test equipment, real estate and timerequired for the fabrication process. Alternatively, the measurementsystem 1820 may comprise a probe test system or an optical tool. Moreparticularly, a comparison of measurements taken from one die 1804 toanother can facilitate an assessment of process drift or other processanomalies. Such information can be utilized, for example, to determinewhich processing conditions (e.g., alignment, illumination, etc.) arenot operating within defined parameters and thus should be looked atmore closely to determine how to rectify an undesirable situation. Thisinformation may also be utilized, for example, to generate feedbackand/or feed-forward data for mitigating registration error and/orbringing critical dimensions within acceptable tolerances.

It is to be appreciated that any of a variety of fabrication components1818 and/or operating parameters associated therewith can be selectivelycontrolled based upon the readings taken by the measurement system 1820.By way of example and not limitation, this can include, but is notlimited to, temperatures associated with the process, pressuresassociated with the process, concentration of gases and chemicals withinthe process, composition of gases, chemicals and/or other ingredientswithin the process, flow rates of gases, chemicals and/or otheringredients within the process, timing parameters associated with theprocess, alignment, illumination, exposure,magnification/de-magnification and/or focusing of items associated withthe process, attributes of polishing and/or etching componentsassociated with the process and excitation voltages associated with theprocess.

By way of further example, parameters associated with high-resolutionphotolithographic components utilized to develop IC's with small closelyspaced apart features can be controlled to mitigate process drift,mis-patterning, registration errors and/or to achieve desired criticaldimensions. In general, lithography refers to processes for patterntransfer between various media and in semiconductor fabrication, asilicon slice, the wafer, is coated uniformly with a radiation-sensitivefilm, the photoresist. The photoresist coated substrate is baked toevaporate any solvent in the photoresist composition and to fix thephotoresist coating onto the substrate. An exposing source (such aslight, x-rays, or an electron beam) illuminates selected areas of thesurface of the film through an intervening master template for aparticular pattern. The lithographic coating is generally aradiation-sensitized coating suitable for receiving a projected image ofthe subject pattern. Once the image from the intervening master templateis projected onto the photoresist, it is indelibly formed therein.

Light projected onto the photoresist layer during photolithographychanges properties (e.g., solubility) of the layer such that differentportions thereof (e.g., the illuminated or un-illuminated portions,depending upon the photoresist type) can be manipulated in subsequentprocessing steps. For example, regions of a negative photoresist becomeinsoluble when illuminated by an exposure source such that theapplication of a solvent to the photoresist during a subsequentdevelopment stage removes only non-illuminated regions of thephotoresist. The pattern formed in the negative photoresist layer is,thus, the negative of the pattern defined by opaque regions of thetemplate. By contrast, in a positive photoresist, illuminated regions ofthe photoresist become soluble and are removed via application of asolvent during development. Thus, the pattern formed in the positivephotoresist is a positive image of opaque regions on the template.Controlling the degree to which a photoresist is exposed to illumination(e.g., time, intensity) can thus affect the fidelity of pattern transferand resulting critical dimensions, patterning and/or registration error.For example, overexposure can create features that are smaller ornarrower than desired (for a positive resist), while underexposure cancreate features that are larger than desired.

The type of illumination utilized to transfer the image onto a wafer canalso be controlled to affect patterning and critical dimensions. Forinstance, as feature sizes are driven smaller and smaller, limits areapproached due to the wavelengths of the optical radiation. As such,that type of radiation and thus the wavelengths of radiation utilizedfor pattern transfers can be controlled to adjust patterning andcritical dimensions and mitigate registration error. For instance,radiation having more conducive wavelengths (e.g., extreme ultraviolet(EUV) and deep ultraviolet (DUV) radiation having wavelengths within therange of 5-200 nm) can be utilized for lithographic imaging in an effortto accurately achieve smaller feature sizes. However, such radiation canbe highly absorbed by the photoresist material. Consequently, thepenetration depth of the radiation into the photoresist can be limited.The limited penetration depth requires use of ultra-thin photoresists sothat the radiation can penetrate the entire depth of the photoresist inorder to effect patterning thereof. The performance of circuits formedthrough photolithographic processing is, thus, also affected by thethickness of photoresist layers. The thickness of photoresist layers canbe reduced through altering resist viscosity and/or employing a higherspin speed during coating.

In general, CMP employs planarization techniques wherein a surface isprocessed by a polishing pad in the presence of an abrasive ornon-abrasive liquid slurry. The slurry employed reacts with thephotoresist at the surface/subsurface range. Preferably the degree ofreaction is not great enough to cause rapid or measurable dissolution(e.g., chemical etching) of the photoresist, but merely sufficient tocause a minor modification of chemical bonding in the photoresistadequate to facilitate surface layer removal by applied mechanicalstress (e.g., via use of a CMP polishing pad). Thus, critical dimensionsand registration can be affected by controlling the concentration, rateof flow and degree of abrasiveness of slurry applied during the CMPprocess as well as the amount of pressure applied between the polishingpad and wafer during the process.

Depending upon the resist system utilized, post exposure baking may alsobe employed to activate chemical reactions in the photoresist to affectimage transfer. The temperatures and/or times that portions of the waferare exposed to particular temperatures can be controlled to regulate theuniformity of photoresist hardening (e.g., by reducing standing waveeffects and/or to thermally catalyze chemical reactions that amplify theimage). Higher temperatures can cause faster baking and fasterhardening, while lower temperatures can cause slower baking andcorrespondingly slower hardening. The rate and uniformity of photoresisthardening can affect critical dimensions, patterning and/orregistration, such as, for example, by altering the consistency of aline width. Accordingly, time and temperature parameters can becontrolled during post exposure baking to affect critical dimensions,patterning and/or registration.

Operating parameters of an etching stage can similarly be controlled toachieve desired critical dimensions and to mitigate registration error.After illumination, the pattern image is transferred into the wafer fromthe photoresist coating in an etching stage wherein an etchant, as wellas other ingredients, are applied to the surface of the wafer by anexcitation voltage or otherwise. The etchant removes or etches awayportions of the wafer exposed during the development process. Portionsof the wafer under less soluble areas of the photoresist are protectedfrom the etchants. The less soluble portions of the photoresist arethose portions that are not affected by the developer during thedevelopment process and that are not affected by the etchant during theetching process. These insoluble portions of the photoresist are removedin subsequent processing stage(s) to completely reveal the wafer and thepattern(s) formed therein. The concentration or electrical charge andenergy of materials utilized in etching can thus be controlled toachieve desired critical dimensions, for instance, by affecting theaccuracy with which selected portions of the wafer can be etched away.

Parameters relating to the type of template utilized to transfer animage onto a wafer can also be controlled to affect critical dimensions,layer to layer alignment and registration error. Where the template is areticle, the pattern is transferred to only one (or a few) die perexposure, as opposed to where the template is a mask and all (or most)die on the wafer are exposed at once. Multiple exposures through areticle are often performed in a step and scan fashion. After eachexposure, a stage to which the wafer is mounted is moved or stepped toalign the next die for exposure through the reticle and the process isrepeated. This process may need to be performed as many times as thereare die in the wafer. Thus, stepper movement can be controlled tomitigate registration error (e.g., by feeding fed forward and/orbackward measurements to a stepper motor).

The pattern formed within the reticle is often an enlargement of thepattern to be transferred onto the wafer. This allows more detailedfeatures to be designed within the reticle. Energy from light passedthrough the reticle can, however, heat the reticle when the image isexposed onto the wafer. This can cause mechanical distortions in thereticle due to thermal expansion and/or contraction of the reticle. Suchdistortions may alter the geometry of intricate features (e.g., bynarrowing a line) and/or interfere with layer to layer registration tosuch a degree that a resulting circuit does not operate as planned whenthe image is transferred onto the wafer. Moreover, since the pattern isusually an enlargement of the pattern to be transferred onto the wafer,it typically has to be reduced (e.g., via a de-magnifying lens system)during the lithographic process. Shrinking an already distorted feature(e.g., a narrowed line) can have a deleterious effect on criticaldimensions. Thus, while such a template may be effective to transfermore intricate pattern designs, it calls for highly accurate alignmentand imaging to mitigate registration errors and maintain criticaldimensions to within acceptable tolerances. Temperature controls canthus be employed to mitigate thermally induced mechanical distortions inthe reticle.

Additionally, parameters relating to film growth or depositioncomponents (e.g., producing metals, oxides, nitrides, poly, oxynitridesor insulators) can be controlled to achieve desired critical dimensions.Such films can be formed through thermal oxidation and nitridation ofsingle crystal silicon and polysilicon, the formation of suicides bydirect reaction of a deposited metal and the substrate, chemical vapordeposition (CVD), physical vapor deposition (PVD), low pressure CVD(LPCVD), plasma enhanced CVD (PECVD), rapid thermal CVD (RTCVD), metalorganic chemical vapor deposition (MOCVD) and pulsed laser deposition(PLD). The rates of flow, temperature, pressures, concentrations andspecies of materials supplied during the semiconductor fabricationprocess can thus be controlled to govern film formation which bears oncritical dimensions.

As mentioned above scanning electron microscope (SEM) or othertechniques can be employed by the measurement system 1820 in accordancewith one or more aspects of the present invention to determine whateffect, if any, the various processing components are having on thefabrication process. Different structure or feature dimensions (e.g.,height, width, depth) may, for example, be measured to generatedifferent signatures that may be indicative of the effect that one ormore processing components are having upon the fabrication process andwhich operating parameters of which processing components, if any,should thus be adjusted to rectify any undesirable processing. Theprocessing components and/or operating parameters thereof may, forexample, be able to be controlled based upon feedback/feed-forwardinformation generated from the measurements. For example, at a firstpoint in time a first signature may be generated that indicates thatdesired critical dimensions have not yet been achieved but aredeveloping within acceptable tolerances, but that registration error isoccurring. Thus, the process may be adapted in an attempt to mitigateregistration error, but not affect developing critical dimensions. Then,at a second point in time a second signature may be generated thatindicates that registration error is no longer occurring or is reduced,but that the desired critical dimensions still have not been achieved.Thus, on another wafer the process may be allowed to continue for alonger time when a corresponding signature indicates that the desiredcritical dimensions have been achieved without the occurrence ofregistration error.

It will be appreciated that the measurement system 1820 can reside inone physical or logical device (e.g., computer, process) and/or bedistributed between two or more physical or logical devices. Themeasurement system includes one or more non-destructive measurementcomponents adapted to take readings of the test structures. Themeasurement system is operatively coupled to the control system that canbe configured in any suitable manner to control and operate the variouscomponents within the system in order to carry out the various functionsdescribed herein. For example, the control system 1816 may provide oneor more signals to the measurement system to control at least some ofthe operations of the measurement system 1818. Similarly, the controlsystem 1816 is adapted to receive signals from the measurement systemindicative of readings taken thereby. Such readings may, for example, berelated to critical dimensions, conductivity, resistivity, etc. of thetest structures.

In the example shown, the control system 1816 includes a processor 1828,such as a microprocessor or CPU, coupled to a memory 1830. The processor1828 can be any of a plurality of processors, and the manner in whichthe processor 1828 can be programmed to carry out the functions relatingto the present invention will be readily apparent based on thedescription provided herein. The memory 1830 included within the controlsystem 1816 serves to store, among other things, program code executedby the processor 1828 for carrying out operating functions of the systemas described herein. The memory 1830 may include read only memory (ROM)and random access memory (RAM). The ROM contains among other code theBasic Input-Output System (BIOS) which controls the basic hardwareoperations of the system 1800. The RAM is the main memory into which theoperating system and application programs are loaded. The memory 1830may also serve as a storage medium for temporarily storing informationsuch as, for example, tabulated data and algorithms that may be employedin carrying out one or more aspects of the present invention. The memory1830 can also serve as the data store 1826 and can hold patterns againstwhich observed data can be compared as well as other data that may beemployed in carrying out the present invention. For mass data storage,the memory 1830 may include a hard disk drive, for example.

It will be appreciated that the control system, and more particularlythe processor, may be operatively coupled to a fabrication componentdriving system (not shown) that drives the fabrication components 1818.The processor 1828 would control the fabrication component drivingsystem to selectively control one or more of the fabrication components1818 and/or one or more operating parameters associated therewith asdescribed herein. The processor 1828 monitors the process andselectively regulates the fabrication process by controlling thecorresponding fabrication components 1818. Such regulation canfacilitate controlling critical dimensions and mitigating mis-patterningand registration error during fabrication and can further facilitateinitiating a subsequent fabrication phase with more precise initialdata, which facilitates improved chip quality at higher packingdensities

It will be further appreciated that training techniques can beimplemented in accordance with one or more aspects of the presentinvention. For example, such techniques can be utilized to populate thedata store 1826 (which may be comprised within the memory 1830) for usein subsequent monitoring. For example, readings taken by the measurementsystem can be utilized (e.g., by the processor) to generatesubstantially unique signatures that can be stored in the data store1826. The data store 1826 can be populated with an abundance ofsignatures, for example, by examining a series of wafers and/or waferdies. Such signatures can, for example, be compared to values obtainedby the measurement system to generate feed forward/backward control datathat can be employed in regulating the fabrication process. It is to beappreciated that the data store 1826 can store data in data structuresincluding, but not limited to one or more lists, arrays, tables,databases, stacks, heaps, linked lists and data cubes. Furthermore, thedata store 1826 can reside on one physical device and/or may bedistributed between two or more physical devices (e.g., disk drives,tape drives, memory units).

It will be still further appreciated that intelligent software can beutilized to detect process margin where spaces, lines and/or otherfeatures disappear or deviate on corresponding die. Process margin ofone or more die on or about the center of the wafer can, for example, becompared to process margin of one or more die on or near an edge of thewafer to determine process margin differences across the wafer.Similarly, process margin at one location (e.g., center) of one wafercan be compared to process margin at corresponding locations on other(e.g., subsequently processed) wafers. A determination can then be madeas to whether process margin is drifting from wafer to wafer. This canalso be done from lot to lot to determine process drift over time.

FIG. 19 is a schematic diagram of a random section of a test module 1900having a plurality of test structures formed therein in accordance withone or more aspects of the present invention. FIGS. 20-22 are similarschematic diagrams wherein some areas 1902 of a wafer that may exhibitproblems if relevant structures are exposed to process drift areencircled in an ellipse. For example, if the geometry of thosestructures is increased, bridging may occur as gaps that separate thestructures are reduced to accommodate additional material. Similarly,some areas 1904 that may exhibit problems if relevant structures aredownsized are highlighted by enclosure within a rectangle.

With reference now to FIG. 23, a methodology 2300 is illustrated forfashioning and utilizing a test module to monitor for process driftand/or other aberrant behavior in a semiconductor fabrication process inaccordance with one or more aspects of the present invention. Althoughthe methodology 2300 is illustrated and described hereinafter as aseries of acts or events, it will be appreciated that the presentinvention is not limited by the illustrated ordering of such acts orevents. For example, some acts may occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein, in accordance with one or more aspects of thepresent invention. In addition, not all illustrated steps may berequired to implement a methodology in accordance with the presentinvention. Furthermore, any methodologies according to the presentinvention may be implemented, to varying degrees, in association withthe formation and/or processing of structures that may or may not beillustrated and described herein.

The methodology begins at 2302 wherein a plurality of test modules areformed within a plurality of die on a test wafer. The test modules,themselves, include a plurality of test structures or test elements. Thetest modules can, for example, have hundreds of different types ofstructures and/or feature combinations located thereon. It will beappreciated that the test structures (and thus the test modules) can besized according to or in increments of design rules. Design rules for aparticular device or integrated circuit may, for example, dictate that aparticular structure or feature within the device is to have a certaindimension (e.g., thickness, width) to ensure that the device performswith a desired reliability.

The test structures of a first test module on a die can thus be formedaccording to one hundred percent of the design rules. The teststructures of a second test module on the die can be formed according toninety seven percent of the design rules. And, the test structures of athird test module on the die can be formed according to ninety sevenpercent of the design rules, etc. It will be appreciated, however, thatthese figures are exemplary only and that the test structures (and thusthe test modules) can be sized according to any variations of designrules. For example, the test structures can be sized so that one or moreof them exceed one hundred percent of the design rules. Sizing the teststructures can enhance sensitivity and facilitates finding thosefeatures that are prone to failures (e.g., shorts or opens) due tovariations in processing conditions, such as alignment, layerthickness/width, layer flatness, layer (non) uniformity, illuminationintensity, focus control, degree of focus, developer conditions, etchcharacteristics (e.g., composition), etc.

The methodology then proceeds to 2304 wherein the test structures withinthe test modules are inspected and compared. A scanning electronmicroscope can, for example, be utilized to inspect the structures. Ameasured value of a test structure or feature in one die can then becompared to a measured value of the same test structure or feature in anadjacent die. If there is a substantial difference or a difference thatcorresponds to a predefined standard, then this may be an indicationthat this particular test structure is sensitive to the instantoperating conditions. By way of further example, an inspection tool canbe utilized to interrogate a first test structure on a first test modulelocated on a first die. The same test structure on a similar test modulelocated on a second die can similarly be inspected. This can be done forany number of structures on any number of test modules located on anynumber of die. Measured values of the same structures taken from similartest modules located on different die can then be compared to determinesensitivity of test structures to operating conditions. Moreparticularly, one or more differences in these values may be indicativeof a structure that is sensitive to changes in processing conditions,process drift or production abnormalities.

At 2306, based upon the foregoing comparisons and determinations, acollection or subset of features or elements that are highly sensitiveto process variations and that are dimensioned so as to have anincreased sensitivity is generated. It will be appreciated that theparticular makeup of the subset of features may be dependent upon theprocess under which the test structures were analyzed. For example, aPMOS process may yield a subset of features different than that producedby an embedded memory process because different processes operate underdifferent conditions. Accordingly, the test structure may be developedunder controlled variations in processing conditions to provide amechanism that is sensitive to particular types of fabricationprocesses. Thus, detected changes in these subsets may be indicative ofprocess drift in particular processing conditions inherent to particulartypes of semiconductor fabrication processes.

Additionally, it will be appreciated that since the subset comprisesless than all of the features in original test modules and may bedetermined utilizing features having dimensions smaller than thosecorresponding to an original design rule, the size of the subset offeatures may be small enough to be formed within a scribe line or otherunused available space (e.g., “white space”) within a production wafer(e.g., on a die, between die, between elements within a die) to monitorfor process drift. The subset of test features would thus have its ownset of design rules that are smaller than production design rules toexpose process variations or drift.

Accordingly, at 2308 relevant subset test modules are incorporated intounused or white spaces within a production wafer. At 2310, the teststructures within the subset test modules are then inspected andcompared to one another to determine if process drift is occurring.Depending upon the type of structures that are affected, the particularfabrication stage (e.g., alignment, illumination) that is drifting orotherwise exhibiting aberrant behavior may be able to identified andmonitored at 2312. The troublesome stage(s) may then be adjusted as isnecessary at 2314 to rectify the situation.

From the foregoing it will be appreciated that one or more aspects ofthe present invention can be utilized to assess existing process flowsfor pattern anomalies, identify process drift, and/or the effects ofmaterial substitutions, etc. and thereby facilitate a reduction inand/or streamlining of the number and/or duration of semiconductorfabrication processing steps, so as to increase product throughput andreduce product cost. Aspects of the present invention may also serve tomaintain the integrity of the processing steps so that semiconductorfabrication processes are carried out within acceptable operatingparameters to facilitate device fabrication in accordance with designrules. Such design rules may, for example, dictate particularcharacteristics to which the devices can be made to ensure certainpredetermined performance characteristics. For example, the design rulesfor a particular device-may dictate that a feature or element within thedevice is to have a particular dimension (e.g., thickness, width) toensure that the device performs with a desired reliability.

Although the invention has been shown and described with respect to oneor more implementations, equivalent alterations and/or modifications maybe evident based upon a reading and understanding of this specificationand the annexed drawings. The invention includes all such modificationsand alterations and is limited only by the scope of the followingclaims. In particular regard to the various functions performed by theabove described components (assemblies, devices, circuits, etc.), theterms (including a reference to a “means”) used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (i.e., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure which performs thefunction in the herein illustrated exemplary implementations of theinvention. In addition, while a particular feature of the invention mayhave been disclosed with respect to only one of several implementations,such feature may be combined with one or more other features of theother implementations as may be desired and advantageous for any givenor particular application. Furthermore, to the extent that the terms“includes”, “having”, “has”, “with”, or variants thereof are used ineither the detailed description or the claims, such terms are intendedto be inclusive in a manner similar to the term “comprising.”

1-15. (canceled)
 16. A test wafer suitable for use in developing one ormore subset test modules that are themselves suitable for use in asemiconductor fabrication process to facilitate a determination ofprocess drift, the wafer comprising: one or more die, wherein therespective die have a plurality of test modules formed thereon that aresubstantially the same from die to die, and wherein corresponding testmodules on the respective die have a plurality of test structures formedthereon that are substantially the same from module to module, andwherein differences in corresponding test structures on correspondingtest modules are indicative of process drift or process sensitivity. 17.The wafer of claim 16, wherein different structures within the testmodules are designed so as to have a heightened sensitivity toparticular processing conditions, thus facilitating generation of one ormore subset modules that enable selective identification of processingconditions that may be drifting.
 18. The wafer of claim 16, wherein thetest structures are formed according to design rules.
 19. The wafer ofclaim 17, wherein the test structures are formed in increments of aboutthree percent of design rules.
 20. The method of claim 16, wherein thesubset modules are small enough to be incorporated within scribe lineswithin a production wafer and/or within white spaces within die on theproduction wafer.
 21. A mechanism suitable for incorporating into aproduction wafer to facilitate a determination of semiconductorfabrication process drift, the mechanism comprising: one or more subsetmodules comprising a plurality of test structures formed thereon,wherein the test structures are sensitive to process drift or otheraberrant processing conditions, wherein the plurality of test structuresare substantially the same among at least some of the subset modules,and wherein detected differences between corresponding test structuresprovide an indication that process drift or other aberrant processingconditions are occurring.
 22. The mechanism of claim 21, wherein thesubset modules are small enough to be incorporated within scribe lineswithin a production wafer and/or within white spaces within die on theproduction wafer.
 23. The mechanism of claim 21, suitable of providing adetermination of at least one of that process drift may be occurringacross the production wafer, that process drift may be occurring fromwafer to wafer and that process drift may be occurring from one waferlot to one or more other wafer lots.